• Full-featured, Native Testbench support for SystemVerilog and OpenVera® testbenches enables the creation of highly effective verification environments using object-oriented techniques, constrained-random stimulus and functional coverage, and provides up to 5X faster verification performance compared with stand-alone testbench tools

   

• Included Synopsys VMM methodology and building-block libraries help accelerate the creation of robust, reusable verification environments following industry best practices for coverage-driven, constrained-random and assertion-based verification techniques

   

• Built-in, complete support for SystemVerilog assertions (SVA) and OpenVera assertions (OVA), a library of over 50 ready-to-use checkers and the VCS Assertion IP Library for many popular interface protocol standards enable fast deployment of an assertion-based design-for-verification (DFV) methodology to speed bug detection and design quality

   

• Built-in, comprehensive coverage metrics and unified coverage reporting aggregate functional, assertion, and code coverage data to provide a single view of coverage attainment against verification goals

   

• Support for all popular design and verification language standards, including Verilog, VHDL, SystemVerilog and SystemC enables higher design and verification productivity and faster integration of complex SoCs built using multiple languages

   

• Powerful debug and visualization environment provides easy access to design and verification data via a flexible-use model incorporating popular drag-and-drop, menu and icon-driven methods for shorter analysis and debug cycles

   

• Industry-leading performance and capacity accelerate verification throughput and time-to-market

   

• Integration within Synopsys Discovery AMS™ solution provides the highest throughput and accuracy for mixed-signal simulations

   

• Integration with other best-in-class Discovery RTL Verification Platform solutions ensures a smooth flow and complete design verification to find bugs quickly and easily.

   

• Fast, native support for DesignWare® verification IP speeds verification of designs incorporating a wide range of standard interface protocols

Full-Featured, Native Testbench and Industry-Leading SystemVerilog Support
VCS Native Testbench (NTB) provides built-in natively-compiled support for full-featured SystemVerilog and OpenVera testbenches including object-oriented, constrained-random stimulus and functional coverage capabilities. Multiple solver engines simultaneously analyze all user-specified constraints to rapidly generate high-quality random stimulus to verify the design for corner-case behavior. These engines will find a solution to user constraints, if one exists, minimizing constraint conflicts and maximizing verification productivity.

Verification Methodology
The VCS solution s powerful testbench engines are complemented by the proven VMM methodology, defined in the popular Verification Methodology Manual for SystemVerilog, and layered testbench architecture that enables both new and experienced verification engineers to quickly create and deploy advanced, reusable, efficient verification environments. This methodology, developed and used by verification experts, helps users adopt industry best practices to get the best possible results from the VCS solution. A detailed reference manual, pre-written testbench building blocks (for both SystemVerilog and OpenVera) and examples are provided with the VCS solution. The VCS Verification Library provides extensive support for the VMM methodology including an object interface and scenario generators.

Complete Assertion Technologies
The native assertion technology in the VCS solution enables an efficient methodology for deploying design-for-verification techniques. The built-in support of SystemVerilog and OpenVera assertions allows designers to easily adopt DFV and find more bugs more quickly. A rich assertion-checker library and a unique library of Assertion IP make it even easier to deploy DFV techniques across teams and improve their verification quality.

The predefined assertion checker library of over 50 assertion checkers makes it very easy for designers and verification engineers to adopt and deploy DFV without a steep learning curve. Each checker抯 implementation can be viewed and customized for the designers?own specific needs.

The VCS Assertion IP Library contains a set of advanced checkers and monitors that enable the verification of correct design behavior for standards-based interface protocols. As a contributor to verification quality, the Assertion IP Library components include built-in functional coverage metrics.

Please contact your local Synopsys representative for Assertion IP titles and availability.

Native Testbench support for the VCS Verification Library speeds verification of designs incorporating the industry抯 most popular bus and I/O standards. The VCS Verification Library provides extensive support for the Reference Verification Methodology (RVM).

Comprehensive Coverage
The VCS solution provides high-performance built-in coverage technology to measure the attainment of the verification goals. The comprehensive code coverage metrics include: line, FSM, condition, toggle and path. The VCS solution also provides assertion coverage to make sure that the assertions are fully exercised during simulation. Functional coverage is also captured with the NTB support for coverage groups and scenarios.

The VCS solution抯 unified coverage makes it easy to capture, aggregate and report coverage information. With VCS, no timeconsuming code coverage instrumentation step is required ensuring maximum ease of use. Coverage technology is natively compiled in the solution, delivering the highest performance and productivity. Auto-grading coverage reports help prioritize the regression runs and even eliminate unnecessary tests. Aggregate reports give a measure of how well the many regression runs are fully testing the design. Finally, VCS coverage report combines code assertion and functional coverage into a single easy to read web-based report.

Advanced Debugging and Visualization Environment
The VCS solution includes the Discovery Visualization Environment (DVE), a new next-generation, full-featured debug and visualization environment. The DVE has been specifically architected to work with all of the advanced bug-finding technology in VCS and shares a common look and feel with other Synopsys graphical-based analysis tools. DVE enables easy access to design and verification data along with an intuitive drag-and-drop or menu-and-icon driven environment. Its debug capabilities include: tracing drivers, waveform compare, schematic views, path schematics, and support for the highly efficient Synopsys compact VCD+ binary dump format.

It also provides elegant mixed-HDL (SystemVerilog, VHDL and Verilog) and SystemC/C++ language debugging windows along with next-generation assertion tracing capabilities that help automate the manual tracing of relevant signals and sequences. TCL support is provided for interaction or batch control and skin / menu customization. A unified command language is supported to provide a common set of commands for all tools, languages and environments making it easy to deploy new technology across design teams. These commands are logged for all actions in DVE and can be modified or replayed easily.