Seismos, a transistor-level design product, is the first in the EDA market to analyze stress and well proximity effects in circuit-level designs in nanometer technologies. The Seismos model originates from TCAD simulations and is validated by silicon data, but the solution primarily aids circuit designers.

Benefits

• Enable circuit designers to simulate and optimize the layout dependency of silicon stress effects on device characteristics and circuit performance
• Handle a wide range of design sizes from a few transistors to multimillions of transistors with high performance and memory efficiency
• Annotate the stress effects back to the SPICE netlist for circuit simulations
• Readily integrate into third-party design flows
• Provide a GUI mode for data visualization and real-time what-if analysis in a layout environment
• Quickly identify complex structures for further analysis in field solvers
• Ensure seamless integration with existing design flows