Mentor.Graphics.ModelSIM.SE.v10.5 ASIC and FPGA design Mentor Graphics was the first to combine single kernel simulator (SKS) technology with a unified debug environment for Verilog, VHDL, and SystemC. The combination of industry-leading, native SKS performance with the best integrated debug and analysis environment make ModelSim® the simulator of choice for both ASIC and FPGA designs. The best standards and platform support in the industry make it easy to adopt in the majority of process and tool flows. ModelSim In Action ModelSim Essentials On-demand Web Seminar Overview Unified mixed language simulation engine for ease of use and performance Native support of Verilog, SystemVerilog for design, VHDL, and SystemC for effective verification of sophisticated design environments Fast time-to-debug, easy to use, multi-language debug environment Advanced code coverage and analysis tools for fast time to coverage closure Interactive and Post-Sim Debug available so same debug environment used for both Powerful Waveform compare for easy analysis of differences and bugs Unified Coverage Database with complete interactive and HTML reporting and processing for understanding and debugging coverage throughout your project Coupled with HDL Designer and HDL Author for complete design creation, project management and visualization capabilities ModelSim PE Simulation Download and Trial Now is your opportunity for a risk free 21-day trial of the industry's leading simulator with full mixed language support for VHDL, Verilog, SystemVerilog and a comprehensive debug environment including code coverage.