Mentor Graphics was the first to combine single kernel simulator (SKS) technology with a unified debug environment for Verilog, VHDL, and SystemC. The combination of industry-leading, native SKS performance with the best integrated debug and analysis environment make ModelSim the simulator of choice for both ASIC and FPGA design. The best standards and platform support in the industry make it easy to adopt in the majority of process and tool flows. ModelSim combines high performance and high capacity with the code coverage and debugging capabilities required to simulate larger blocks and systems and attain ASIC gate-level sign-off. Comprehensive support of Verilog, VHDL, and SystemC provide a solid foundation for single and multi-language design verification environments. The ModelSim vopt usage mode achieves industry-leading performance and capacity through very aggressive, global compile and simulation optimization algorithms of Verilog and VHDL, improving Verilog and mixed VHDL/Verilog RTL simulation performance by up to 10X. The performance mode can also improve Verilog gate-level performance by up to 4X and capacity by over 2X. ModelSim also supports very fast time-to-next simulation and effective library management while maintaining high performance with its new black box use model, known as bbox. With bbox, non-changing elements can be compiled and optimized once and reused when running a modified version of the testbench. bbox delivers dramatic throughput improvements of up to 3X when running a large suite of testcases.