High Level Synthesis High Level Synthesis reduces the manual effort required to create and completely verify synthesizable RTL code. Design size and complexity continue to push traditional RTL design and verification methodologies to their limits. Catapult C Synthesis Full-Chip High-Level Synthesis Catapult C Synthesis is a high-level synthesis tool for ASIC and FPGA hardware designers who need to deliver optimal implementations with aggressive time-to-market requirements. Traditional hardware design methods that require hand-written RTL development and debugging are too time-consuming and error prone for today’s complex designs. Catapult C empowers designers to use industry standard ANSI C++ and SystemC to describe functional intent and move up to a more productive abstraction level. From these high-level descriptions, Catapult C generates production quality RTL. With this approach, full hierarchical systems comprised of both control blocks and algorithmic units are implemented automatically, eliminating the typical coding errors and bugs introduced by manual flows. By speeding time to RTL and automating the generation of bug-free RTL, the Catapult C Synthesis tool significantly reduces the time to verified RTL.