High Performance and Capacity Mixed HDL Simulation - ModelSim Mentor Graphics was the first to combine single kernel simulator (SKS) technology with a unified debug environment for Verilog, VHDL, and SystemC. The combination of industry-leading, native SKS performance with the best integrated debug and analysis environment make ModelSim the simulator of choice for both ASIC and FPGA design. The best standards and platform support in the industry make it easy to adopt in the majority of process and tool flows. ModelSim Spotlight ** New Product - ModelSim DE ** With ModelSim DE, we now offer support for Xilinx SecureIP and Assertion-Based Verification with SystemVerilog and PSL support. Find out about Assertion-Based Verification in the Verification Academy. Learn more about ModelSim DE then view the archived web seminar - Introducing ModelSim DE. Featured Event ABV for FPGA and IC Design Seminar You will learn: ~ Assertion-Based Verification techniques ~ Roadmap for evolving your organizations ABV Capabilities ~ Degugging with Assertions ~ Effective Coverage techniques ~ Process for analyzing your data and providing both detailed and management level reports Location and Date: ~ Irvine, CA - June 29th ~ San Diego, CA - June 30th Learn more and register. ModelSim * ModelSim PE * ModelSim DE * ModelSim SE * ModelSim Student Edition Get ModelSim DE * Go Evaluate ModelSim DE