Mentor Graphics Corporation (NASDAQ: MENT) today announced that the Calibre® nmLVS product now provides comprehensive support for the iLVS interoperable rule specification used by TSMC for new design kits. This allows customers to define and customize complex IC design rules, as needed, while maintaining compliance with TSMC specifications and allowing seamless adoption of EDA vendor performance optimizations. The iLVS specification, which was co-developed by Mentor, TSMC and several other EDA partners, separates the rule definition syntax from underlying rule implementations. This allows Mentor to optimize the underlying implementation, reducing the need for users to tune the general rule specifications themselves. Moreover, by using iLVS in conjunction with the Calibre nmLVS Advanced Device Properties (ADP) facility, the Calibre tool users can also establish modules for device building, enabling device model reuse and simplifying model customization for unique parameters. Previously, such customizations required manipulation of detailed SVRF scripts. The iLVS syntax is one of two definitions jointly developed by TSMC, Mentor Graphics, and other EDA partners—iDRC, and iLVS—for describing physical verification and layout vs. schematic (LVS) rules. In addition, Mentor is also supporting TSMC’s iRCX syntax so mutual customers have a complete set of interoperable verification solutions from Mentor. The interoperable definitions make it possible for TSMC and its customers to create verification decks that will work with the Mentor Calibre tool offerings as well as other verification products that support the specification. They also make it possible for Mentor to independently optimize the implementations to maintain performance to end users as the underlying process rules are updated by TSMC.