WILSONVILLE, Ore., Feb 14, 2010 - Mentor Graphics Corporation (Nasdaq: MENT) today announced the availability of Calibre® xRC™ and Calibre xL rule decks for TSMC’s advanced 65nm process node. These rule decks provide advanced modeling capabilities including process sensitivity, and self and mutual inductance. Calibre now provides a solution for many types of integrated circuit designs including analog, digital, mixed signal, and memory.

For nanometer designs, accurate simulation and analysis requires more than traditional resistance and capacitance. Designers need a post-layout silicon model that incorporates inductance, process sensitivity effects, and efficient accounting of effects not captured in the device model. Using Calibre xRC and Calibre xL in the design flow helps ensure that designers have all the data they need to obtain successful first pass silicon.

“We have developed testing methodology for parasitic extraction tools to make sure we deliver accurate solutions to our customers. Calibre xRC and Calibre xL performed well in our internal tests and offers advanced modeling capabilities to capture process variation effects that are necessary for 65nm,” said Ed Wan, senior director of design services marketing, TSMC.

“Delivering accurate, complete parasitic models is an integral part of Calibre’s overall objective to improve silicon yield,” said Joe Sawicki, vice president and general manager, Design to Silicon Division, Mentor Graphics. “When coupled with Calibre LVS for device modeling, Calibre xRC and Calibre xL helps designers address parametric yield issues by accurately capturing process variation effects in device and interconnect models. Additionally, customers now have access to a full complement of inductance models with self, mutual and skin effect modeling that is necessary for today’s high frequency interconnect.”