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Mentor Graphics® Corporation (Nasdaq: MENT), the market and technology leader in printed circuit board (PCB) design solutions, today announced the immediate availability of HyperLynx® 7.7, the latest version of its powerful and easy-to-use tool suite for pre- and post-layout signal integrity (SI) simulation and analysis. HyperLynx 7.7 includes significant productivity and technology enhancements targeted at classic high-speed bus technologies, as well as the rapidly emerging SERDES (SERialization/DE-Serialization) interconnect standards for connecting serial drivers and receivers.

“I use HyperLynx because it is one of the few accurate circuit simulators with coupled lossy-line models and an integrated 2D field solver,” said Dr. Eric Bogatin, industry expert and author of Signal Integrity Simplified. “Plus, it is far and away the quickest tool on the market to learn with a five minute learning curve. With the release of HyperLynx 7.7, its value for high-speed serial link analysis has more than doubled.”

“Gigabit SERDES interconnects are the industry’s answer for faster data transfer,” said Henry Potts, vice president and general manager of Mentor Graphics Systems Design Division. “At current multi-gigabit rates, the ability to simulate is a necessity. HyperLynx 7.7 is a further example of Mentor’s commitment to technology leadership. The release of HyperLynx 7.7 is specifically targeted at increasing design productivity and efficiency for SERDES simulation.”

HyperLynx 7.7 Enhancements
HyperLynx 7.7 provides several industry-leading enhancements, including:

• The integration of Mentor’s mixed-signal simulation engine, enabling simultaneous simulation of AMS, Eldo® (SPICE), IBIS IC models, SPICE package models and frequency-dependent S-parameter models in the same channel
• A Touchstone model viewer, enabling engineers to examine S-parameter models and to quickly check for causality and passivity violations-common problems with these models
• Mentor’s industry-leading complex-pole fitting algorithms which allow large S-parameter files to be compiled natively for Mentor simulators producing an order of magnitude increase in simulation speed
• A pre-layout tool offering complete padstack editing, giving the engineer the ability to compare through-hole, blind or buried vias during channel analysis before going to layout
• A new “fast eye diagram” capability for SERDES design that incorporates Bit Error Rate (BER) prediction and bathtub curves, saving time by enabling engineers to examine eye quality across millions or even billions of cycles in just a matter of minutes
• The unique ability to predict the worst-case bit stimulus sequence that would produce a maximally closed eye diagram

Productivity enhancements include:

• Significant oscilloscope improvements and an extensive upgrade to the batch simulation utility
• The ability to view current waveforms, import/export functionality with Mentor’s Waveform Analyzer and EZWave™ waveform viewers, and ten automated scope measurements that include flight-time, eye width and height and DDR2 de-rating
• Post-layout batch simulation with user-requested features, such as reusable electrical rule sets, wildcard searches for groups of nets, sorting of nets by driver edge rate and batch auditor