Mentor Graphics was the first to combine single kernel simulator (SKS) technology with a unified debug environment for Verilog, VHDL, and SystemC. The combination of industry-leading, native SKS performance with the best integrated debug and analysis environment make ModelSim® the simulator of choice for both ASIC and FPGA designs. The best standards and platform support in the industry make it easy to adopt in the majority of process and tool flows. Overview Unified mixed language simulation engine for ease of use and performance Native support of Verilog, SystemVerilog for design, VHDL, and SystemC for effective verification of sophisticated design environments Fast time-to-debug, easy to use, multi-language debug environment Advanced code coverage and analysis tools for fast time to coverage closure Interactive and Post-Sim Debug available so same debug environment used for both Powerful Waveform compare for easy analysis of differences and bugs Advanced code coverage and analysis tools for fast time to coverage closure Unified Coverage Database with complete interactive and HTML reporting and processing for understanding and debugging coverage throughout your project Coupled with HDL Designer and HDL Author for complete design creation, project management and visualization capabilities


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