Intel Quartus Prime Standard Edition 17.0 What’s New in Quartus Prime Design Software v17.0? Faster Timing Closure with Incremental Block-Based Compilation Flow The Quartus Prime Pro Edition design software v17.0 offers the new Incremental Block-Based Compilation and Design Block Reuse flows, which allow your geographically diverse development team to collaborate on a design. Team members can architect the design into segments, then individually develop and achieve timing closure on each partition of the design. Bringing the global design together is simple since each block maintains its placement and timing. With these features, you can preserve, empty, or export the contents of a partition. A partition that has been preserved, emptied, or exported is called a design block. Using design blocks introduces the concepts of Block-Based Compilation and Design Block Reuse. Incremental Block-Based Compilation is preserving or emptying a partition within a project. This works with core partitions and requires no additional files or floor planning. The partition can be emptied, preserved at Source, Synthesis, and Final snapshots. Easier Collaboration with Design Block Reuse Flow The Quartus Prime design software v17.0 offers the new Design Block Reuse flow, which enables a user to reuse a block of a design, in a different project, by creating, preserving, and exporting a partition. With this feature, you can expect a clean hand off, of timing-closed modules between different teams. It also gives you the flexibility of placing timing-closed blocks, pre-built components or even 3rd party IP. Two types of block reuse are supported in this flow - core logic partition and periphery partition. The Periphery Reuse flow allows you to reuse a placed and routed periphery (including I/O, HSSIO, PCIe*, phase-locked loops (PLLs), as well as core resources) and leave an empty (flexible) development area open for other designers. The empty area is defined by a special type of partition that creates a hole in the periphery. This hole can be developed later by another team. Reduced Full Design Iterations with Early Placement Stage The incremental optimization capability in the Quartus Prime Pro Edition software offers a faster methodology to converge to design sign-off with a new Early Placement stage. The traditional fitter stage is divided into finer stages for more control over the flow in the Quartus Prime Pro Edition software: Plan stage allows legal placement and clock planning, along with timing analysis on preliminary I/O and HSSI to FPGA fabric transfers Placement stage enables timing analysis before proceeding to the Route stage. The Placement stage is split into an Early Placement stage and a final placement stage: Perform timing analysis after the Early Placement stage Chip planner provides a visual view of the Early Placement stage Route is split into Route and Post-Route stage for faster design convergence. 3-corner timing analysis after route, and 4-corner timing analysis after post-route reduces compile time. The post-route stage offers an Engineering Change Order (ECO)-like flow where setup and hold failures are automatically fixed, thus reduces compile time. High-speed or low-power tile optimization is performed in the Post-Route stage.