Quartus® II software version 10.0, the industry's #1 software in performance and productivity for CPLD, FPGA, and HardCopy ASIC designs, is now available. Download Quartus II software today! Version 10.0 supports Altera's new high-performance, built-for-bandwidth devices: Stratix® V GX and GS FPGAs with integrated 12.5-Gbps transceivers. Stratix V GX FPGAs are optimized for high-performance, high-bandwidth applications. Stratix V GS FPGAs target high-performance, variable-precision digital signal processing (DSP) applications with the industry-first variable-precision DSP block. Future Quartus II software releases will also support partial reconfiguration, a Stratix V FPGA feature that reduces power, cost, and board space with more effective logic planning. Version 10.0 continues to deliver Quartus II software's productivity advantage: 2X-3X faster compile times than the nearest competitor for high-density designs New transceiver toolkit with real-time transceiver interface and bit-error rate testing capability Expanded Rapid Recompile support for more compile-time savings with better timing preservation Enhanced QXP file for creating and maintaining an internal custom intellectual property (IP) library for design reuse New Self-Service Licensing Center, your one-stop shop for all software and IP license needs Straix V GX / GS FPGA Support Quartus II software version 10.0 demonstrates distinct performance and productivity advantages with Stratix V FPGAs. Software enhancements plus the Stratix V FPGA architecture deliver advantages that the nearest competitor cannot: 2X-3X faster compile times Two full speed-grade advantage, on average Greater than 90 percent logic utilization 30 percent lower power (vs. previous-generation devices) Get more information at the Stratix V device page. Quartus II software offers complete design flow support for Stratix V FPGAs, including: Advanced place-and-route algorithms enabling industry-leading compile times and the highest logic utilization TimeQuest timing analyzer for easier timing closure Incremental compile to finish designs faster and get started in using partial reconfiguration PowerPlay power optimization for automatic minimization of power consumption SOPC Builder and DSP Builder for faster system design development MegaCore® function IP library for reducing design and test time