Quartus® II software v12.0, the industry's number one software in performance and productivity for CPLD, FPGA, SoC FPGA, and HardCopy® ASIC designs, is now available for download. This version continues to provide an industry-leading productivity advantage by delivering up to 4X faster compile times for 28-nm high-density FPGA designs compared to the previous release. The Quartus II software v12.0 also includes initial support for the ARM-based Cyclone® V SoC FPGA as well as expanded support for the latest 28-nm devices–the Stratix® V, Arria® V, and Cyclone V devices. ndustry-Leading Compile Times For almost a decade, the Quartus II software has consistently delivered the industry’s fastest compile times for high-end FPGAs, averaging a 20 percent reduction annually. The Quartus II software features, such as integrated synthesis, advanced place-and-route algorithms, multiprocessor support, and TimeQuest timing analyzer have all helped with the continuous improvements. This release is yet another example of Altera’s continuous focus on reducing compile times. Figure 1 shows the relative compile time improvements across the Quartus II software releases. The Quartus II software v12.0 delivers significant improvements in compile times for 28-nm devices compared to the previous release. With this release, designs targeting Stratix V FPGAs will see on average a 35 percent reduction in compile times along with an increase in fMAX performance. In addition, designs targeting Cyclone V and Arria V FPGAs will see on average a 25 percent reduction in compile times. Qsys System Integration Tool Enhancements to Altera’s Qsys system integration tool provide improved system design and simplified design reuse for customers. Qsys is based on network-on-a-chip (NoC) technology and allows users to efficiently build hierarchical systems by connecting systems and intellectual property (IP) together. Qsys supports industry-standard interfaces including the Avalon® and ARM® AMBA® AXI™ interfaces, and allows users to mix and match IP cores of different interfaces into their designs. The latest release of Qsys adds support for the AXI-3 interface protocol and includes additional ease-of-use features including: System scripting application programming interface (API) support PCI Express® (PCIe®) Gen3 x4 IP support in Qsys Cyclone V SoC FPGA Device Support SoC FPGAs integrate an ARM-based hard processor system (HPS) consisting of processor, peripherals, and memory interfaces with the FPGA fabric using a high-bandwidth interconnect backbone. These devices combine the performance and power savings of hard IP with the flexibility of programmable logic. Support in the Quartus II software v12.0 includes: Initial Cyclone V SX SoC FPGA compilation support AXI interface support in Qsys Hardware processor system (HPS) interface bus functional models HPS external memory controller simulation HPS peripheral I/O pin selection and validation