Quartus® II software version 11.0, the industry's number one software in performance and productivity for CPLD, FPGA, and HardCopy® ASIC designs is available for download. Quartus II software version 11.0 delivers the production release of Altera’s new system-level integration tool known as Qsys. The Qsys system integration tool saves time and effort in the FPGA design process by enabling faster system development and design reuse. This version delivers expanded support for the Stratix® V FPGA family including added transceiver modes and features. Quartus II software version 11.0 also delivers faster board bring-up with improved debug solutions. These improvements include new performance monitoring capabilities in the external memory interface toolkit and improved usability with the Transceiver Toolkit. Download the Quartus II software v11.0 Subscription Edition or Web Edition today. Qsys System-Level Integration Tool Qsys further improves the productivity of FPGA designers by building on top of the success of SOPC Builder with new system development features and a new high-performance interconnect. Qsys provides many benefits to FPGA designers including: Faster development with automatic interconnect generation, and available plug-and-play Qsys Compliant intellectual property (IP) cores. Altera and its IP partners provide many Qsys Compliant IP cores including interface protocols (e.g. PCI Express®), memories (Eeg. DDR3), processors (e.g. Nios® II processor), and video and image processing megafunctions (e.g. Deinterlacer) Faster timing closure with the high-performance Qsys interconnect based on a network-on-a-chip (NoC) architecture The Qsys interconnect with automatic pipelining delivers up to 2X higher performance compared to SOPC Builder Improved design reuse with support for standard interfaces and hierarchy, so designers can reuse a system generated by Qsys as a subsystem in another Qsys system Faster verification with automatic testbench generation, available suite of verification IP and support for on-chip debug using read and write transactions