Apache Design Solutions RedHawk v19.0.3 For Linux

• Electronic Power and Thermal Management
  This paper presents a comprehensive set of tools and methodologies that can contribute to addressing the challenges of thermal and power management encountered in next-generation unmanned systems

• Advanced Modeling Technologies for Chip, Package, System Co-analysis and Co-optimization
  The traditional approach to chip-package-system (CPS) co-analysis and co-optimization lacks required accuracy and limits productivity. To meet the increasing demands for system cost down calls for a new methodology that is more comprehensive. This white paper outlines the Chip Power Model (CPM™) technologies and solutions available from Apache Design Solutions to help address the CPS convergence challenge.

• Power Noise Analysis for Next Generation ICs
  This paper describes the challenges associated with power delivery network designs and how RedHawk, a full-chip dynamic power analysis tool helps designers address the design failures caused by dynamic power noise.

• Low Power Design Analysis
  This paper describes the technology and methodology for analysis of designs utilizing power-gating switches for leakage control. It describes the requirements of verifying low power designs in different modes of operation, as well as in mixture of various states.

• Power Closure Flow
  This paper describes a power aware physical design methodology that includes power supply planning, resource allocation, and design (package, decap, and power grid network) in conjunction with sign-off quality verification to achieve faster design closures.

• Jitter & Critical Path Timing
  This paper describes the technology behind Apache's PsiWinder, which delivers standard-cell capacity and ease-of-use with Spice-accurate simulation of critical timing paths and clock tree network, including effects such as crosstalk and dynamic voltage drop.

• PathFinder™: Solution for Full-chip IC ESD Integrity
  This paper describes how PathFinder helps designers meet ESD guidelines and identify “weak” areas of the design (layout or circuit) most vulnerable to ESD failures. It also demonstrates how PathFinder can be used for early prototyping and design exploration, especially when clamp cells are inserted inside the core region of the chip.

• Power and Signal Line Electromigration Design and Reliability Validation Challenges
  This paper describes EM integrity analysis for power and signal lines. It outlines the various process and design trends that are increasing the likelihood of EM induced failures in a design and looks at conventional verification techniques for EM integrity and contrasts those with what is required for advanced process nodes.

• Technologies for Power, Signal, Thermal, and EMI Sign-off
  This whitepaper discusses the challenges associated with designing smaller, faster, and lower cost products and the necessity for an analysis methodology that addresses the cross domain effect in today's advanced process designs. The paper also provides an overview of Apache's power and noise solutions and how these products enable comprehensive chip-package-system convergence flow across multiple design discipline