Altera’s Quartus® II software is the industry's number one software in productivity and performance for CPLD, FPGA, and SoC designs. Quartus II software v13.1 enables you to achieve unprecedented levels of design productivity by enabling more design iterations within a day, and providing the tools to capture your design intent in the most efficient way possible. With Quartus II software v13.1, you will experience an average of 30% reduction in compile time and an additional average of 50 percent reduction for small design changes, enabling quicker design turns and faster time to market. In addition, Quartus II software v13.1 provides new capabilities, enhancements, and performance improvements to our suite of higher level design tools (i.e. Qsys, OpenCLTM, and DSP Builder) to efficiently capture your design intent, providing IP-based, C-based, or model-based entry. Download Quartus software What's New Delivering the Industry's Fastest Compile Times With Quartus II software v13.1, you can achieve an average of 30% and up to 70% percent reduction in compile times compared with the previous version without compromising fMAX performance. In addition, when making small, non-timing critical changes on large Stratix® V FPGA designs, the newly available Rapid Recompile feature can further achieve 50 percent reduction in compile times compared to a full compilation. Altera continues to focus and commit in delivering the industry’s fastest compile times. Quartus II software v13.1 makes significant improvements on algorithm optimization and parallelization on the algorithm, and scale even better with the number of cores on your multiprocessor machine. Figure 1 illustrates the benchmark results on high-end devices in the Quartus II software since 2011. Figure 1: Relative Compile Times for High-End FPGAs Normalized to 2011 Improving algorithm optimization and parallelization enables the Quartus II software to maintain its leadership in compilation time. Figure 2 shows the Quartus II software v13.1 compile time comparison with the nearest competitor. Figure 2: Compile Time Comparison in Quartus II v13.1 vs. Competing Design Tools Rapid Recompile is a push-button feature that allows you to reuse previous compilation results to reduce compilation time without requiring up-front design partitioning. Rapid Recompile can also reduce timing variation between successive compilation by automatically preserving the original placement and routing of portions of the design that have not been modified between compilations. Figure 3 shows the results of using Rapid Recompile to make several small design changes to a very large Optical Transport Network (OTN) design targeting the Stratix V FPGA device. In this design, Rapid Recompile is able to implement each design change with very little disruption to the design’s overall final fMAX result. Figure 3: Rapid Recompile Enables Faster Design Cycle while Preserving Performance