The ISE® Design Suite: Logic Edition includes exclusive tools and technologies to help achieve optimal design results. These include Intelligent Clock-Gating for dynamic power reduction, Team Design for multi-site design teams, Design Preservation for timing repeatability, and Partial Reconfiguration for greater system flexibility, size, power and cost reduction ISE Simulator (ISim) ISim provides a complete, full-featured HDL simulator integrated within ISE. HDL simulation now can be an even more fundamental step within your design flow with the tight integration of the ISim within your design environment. ISE Simulator ISim Key Features: Mixed language support Supports VHDL-93 and Verilog 2001 Native support for all HardIP blocks PPC, MGT, PCIe, etc. No special license requirements Supports AXI Bus Functional Model (BFM) Multi-Threaded compilation Post-Processing capabilities Tcl scriptable GUI and batch mode simulation run Standalone Waveform viewing capabilities Debug capabilities Waveform tracing, waveform viewing, HDL source debugging Power Analysis and optimization using SAIF Memory Editor for viewing and debugging memory elements Single click re-compile and re-launch of simulation Integrated with ISE Design Suite and PlanAhead application Easy to use - One-click compilation and simulation Hardware Cosimulation capability Offload a design or a portion of the design to hardware Accelerate RTL simulation by up to 50x Xilinx simulation libraries “built-in” Additional mapping or compilation not required