Atrenta launched version 4.5 of their SpyGlass product family. SpyGlass 4.5 features improvements in usability, debug, advanced linting, power estimation and reduction, CDC verification, constraints management, and testability. SpyGlass v4.5 is now in production and available for download. Atrenta’s SpyGlass solution methodology provides a structured, easy to use and a comprehensive method for solving RTL design issues. Atrenta SpyGlass 4.5 Highlights * Industry-standard Tcl command line interface * RTL designers can create specialized scripts for repetitive tasks, perform interactive query and exploration, debug interactively and generate/customize reports * Additional abstractions in the incremental schematic enables engineers to focus on the specific logic related to a violation * Features concept of scenarios for more intuitive analysis and management of configurable and/or multi-mode designs * SpyGlass CDC features structural analysis technology for accelerating the process of identifying and resolving clock domain crossing (CDC) problems * Techniques to pin-point only the real CDC issues in a design and minimize the effort required to debug and fix them * New hierarchal CDC analysis capability uses an abstracted model for already analyzed blocks * Virtually unlimited capacity to handle very large SoC designs * SpyGlass Constraints offer run times which are at par with typical static timing analysis (STA) tools for netlist designs * Reported performance improvements of up to 5X * Performance improvements for identifying clock to clock false paths — both the synchronous and asynchronous varieties * SpyGlass DFT and SpyGlass DFT DSM offer the verification of IEEE 1149.1 and IEEE 1500 setup sequences through high-level Tcl commands * SpyGlass DFT DSM supports the CPF and UPF power intent formats for verifying power management circuitry under test mode conditions * SpyGlass MBIST supports a Tcl-based flow for RTL memory built-in self test insertion * SpyGlass Power supports both the CPF and UPF power intent formats * Performance of power verification has been improved (by over 30% in many cases) * RTL power estimation and reduction capabilities support newer techniques to reduce more power around registers and memories * 40% reduction in power on representative customer designs * SpyGlass Power employs both sequential equivalence checking and formal technology * SpyGlass DashBoard and DataSheet reports have a simplified report structure for easy portability