TimingDesigner is a flexible, interactive timing analysis and diagram tool. Its intuitive use of timing diagrams and patented spreadsheet technology allow users to model their unique timing challenges, analyze a range of conditions, obtain accurate results as well as monitor and manage timing margins throughout the design process Cadence Allegro PCB Signal Integrity (SI) Interface TimingDesigner® 9.2 now provides a seamless integration with Cadence® Allegro® PCB SI to aide in more accurate timing analysis. Joint signal integrity and timing analysis is becoming increasingly important as design speeds grow, margins shrink, and project schedules shorten. This enhanced integration allows users to import simulated interconnect delays from Allegro PCB SI, enabling design teams to resolve timing issues early in the design process when the cost of change is the lowest. Benefits: * Accurate analysis through patented TimingDesigner algorithms combined with Cadence Design Systems signal integrity simulation technology * Graphical view of signal integrity affected timing margins makes it easy to see and repair violations * Template files enable fast updates of SI results as design iterations occur * Flexible timing models supports easy re-use among designs Generate SDC Timing Constraints The introduction of version 9.1 made TimingDesigner the only tool that could generate SDC timing constraints from a timing diagram. This enabled users to visually define design requirements and then automatically generate SDC to drive place and route. The latest TimingDesigner 9.2 release continues this development initiative by providing better support for multiple SDC variants, SDC management, and auto-generation of constraint values based on downstream requirements. SDC is an open source industry standard timing constraint format supported by most FPGA and ASIC design flows. Allowing users to generate SDC constraint files from a timing diagram reduces the complexity of the SDC constraint format, while providing users a visual verification that their constraints are specifying the desired design intent.