provides fast visualization of RTL, so that an engineer can easily understand, and implement existing code elements, whether in VHDL, Verilog or System Verilog. It is no longer possible to carry out all ASIC and SoC designs from scratch: elements of previous designs have to be re-used and third party IP blocks are embedded very often. But understanding the RTL for third party IP or legacy code is not always easy, making it time consuming and difficult to modify and integrate into the new design.