G ateVision PRO is the third generation of graphical net- list analyzers from Concept Engineering. Completely rewritten to run on 32/64bit platforms, GateVision PRO provides the designer of even the largest chips with intuitive design navigation, schematic viewing, logic cone extraction and interactive logic cone viewing for debug support and design docu- mentation. Using Verilog or EDIF netlists, GateVision Graphical netlist analyzer − Verilog or EDIF netlists PRO fits seamlessly into any design environment. The power of the under- Tcl based UserWare API – for advanced customization lying algorithms allows schematics to be 32/64 bit database handles today’s largest SoCs, ASICs and FPGAs created on the fly and the intuitive GUI Intuitive GUI for ease of use lets the designer search for critical paths, Customizable path extraction engine finds critical paths for paths between specific components Cone view extracts schematic fragments of critical areas or for specific areas in the design. These can be bookmarked for future use, or API − a tcl based UserWare API provides full access to the new 32/64-bit cross-probed between different design based database, for highly flexible customization. The designer can extend the views. functionality of GateVison PRO to meet the immediate needs of the project, adding, for example, electrical rule checking (ERC), report and documentation functions. The API also allows GateVison PRO to be closely integrated with different design flows and third party tools.