SGvision PRO 4.7.1 Win is an easy-to-use, very high performance and high capacity tool that is customizable via a tcl-based UserWare API (application programming interface), which allows designers to extend the functionality of SGvision PRO to meet the immediate needs of the project.

• Mixed mode graphical analyzer — Verilog and SPICE in a single tool.
• As detailed as you want — Debugging at gate-level and transistor-level.
• Logic cone — debug selected fragments or critical paths.
• 32/64 bit database — handles the largest SoCs and ASICs.
• Tcl based UserWare API — for advanced customization.
• Cookie cutting — SPICE fragments can be saved as separate SPICE files.

Tcl based API — he Tcl Based UserWare API provides very flexible customization options, allowing SGvision PRO to match individual needs, corporate standards or to be integrated into an organizations design flow.

Customer driven — users of the existing Concept Engineering debugging tools, GateVision® PRO for gate-level and SpiceVision® PRO for transistor-level, have asked for a single interface for mixed level debugging. SGvision PRO provides just this tool, combining two tools in one for flexibility and power in debugging.

32/64 bit — SGvision PRO runs on powerful 64 bit platforms, such as UltraSPARC, Opteron, Itanium and Xeon. The underlying database, specially developed for 32/64 bit operation, allows even the most complex of today's SoC and ASIC designs to be examined.

Documentation — The automated documentation feature of RTLvision PRO provides detailed design documentation of new, changed and re-used code, all to the same standard.

Circuit fragment debugging — the Logic Cone Window is an intelligent magnifying glass, allowing the engineer to concentrate on a specific circuit fragment or critical path, showing both gate- and transistor-level details in a single window. There is no distraction from irrelevant graphics and information, yet there are links to the source code, whether Verilog or SPICE. The fragment under investigation can be independently exported as a SPICE netlist and can be used for the fast simulation of critical circuit fragments. It is not necessary to simulate the whole design, reducing simulation and development time drastically.

Improved productivity — being able to analyze both gate-level and transistor-level at the same time in just one debug cockpit increases design and verification engineers productivity, reducing product development and debug cycle time.