Certify® ASIC prototyping solution is the leading product for ASIC prototyping using multiple FPGAs. Certify software combines RTL multi-chip partitioning with best-in-class FPGA synthesis. Using the Certify product makes ASIC prototyping significantly easier, shortens prototype development time, improves prototype performance, and enables faster time-to-market.

Synplicity has also updated its Partners in Prototyping program to include new off-the-shelf board and design services companies. Synplicity works closely with these companies to verify interoperability between its own products and the Certify tool in order to develop a smooth flow for ASIC designers, system designers and IP developers.

How to Speed ASIC Functional Verification
Functional verification is considered by many the most time consuming task in ASIC design. Companies often use server farms using dozens of copies or more of software simulators running tests or very expensivie hardware emulators to verify their ASIC designs. However, FPGA-based prototypes can offer performance often 20x faster than the fastest emulators.

Prototypes can deliver near realtime speeds for many applications such as wireless communication designs, HW/SW applications, and video or audio based designs. Previously the effort to develop a hardware prototype prevented companies fromusing this methodology. Tools such as the Certify product and off-the-shelf multi-FPGA prototyping boards can now provide a near push-button flow to allow designers to gain the significant benefits of prototypes for verification.

Four Easy Steps to a Prototype
ASIC designs often include elements that need to be converted to an appropriate form for an FPGA implementation such as ASIC gate-level components, or gated-clock tree structures. These elements can be very difficult and time-consuming to edit manually but Certify software provides automatic recognition and translation of these design elements.

Partitioning a design is often difficult unless the design has been planned for it or the designer doing the partitioning is very familiar with it. The Certify solution provides automatic RTL partitioning technology that can be used fully automatic or as a mix of automatic and manual partitioning. The Certify product also includes I/O pin multiplexing technology to allow pins to be shared preventing the common problem of running out of I/O pins. Read more on Quick Partitioning Technology, a new automatic RTL partitioning capability first introduced in Certify 5.0 software.

Since the purpose of prototyping is verification, it is often necessary to view the states of signals internal to the FPGAs. The Certify software provides four different mechanisms for debug logic insertion; probes, multiplexed probes, RTL support for Xilinx ChipScope, and RTL support Altera SignalTap.

Once the design is ready to finish and synthesis, performance is often the final criteria for the prototype. The Certify solution offers the unique ability to optimize timing paths for performance even when those paths cross multiple FPGAs. The Certify product can also provide a timing report letting the designers know the performance possible with the prototype before programming the hardware.