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The CoreConsole IP Deployment Platform (IDP) and block stitcher has been developed to enable designers to quickly assemble system-level designs and to simplify the construction of a processor subsystem and assembly of IP blocks within a design. The CoreConsole IDP is a front-end design entry tool that enables IP blocks to be stitched together into synthesizable and simulatable RTL that can be exported into Actel’s world-class Libero IDE FPGA development tool suite. The CoreConsole IDP  enables users to focus on the system rather than individual components, allowing them to evaluate system-level performance earlier in the design process and reduce overall development time.