Description
Xtensa Xplorer is the only SOC design environment that integrates software development, processor optimization and multiple-processor system-on-chip (SOC) architecture tools into one common platform. You can access powerful design automation tools that ease the creation of Xtensa processor-based SOC hardware and software.
The Xtensa Xplorer IDE serves as the cockpit for the entire design process and provides all the tools necessary for processor and TIE development, software development, and modeling and simulation.
Tensilica’s Xtensa Xplorer GUI serves as the cockpit for the entire design
experience. From Xtensa Xplorer, you can profile your application code, identify “hot spots” that can benefit from acceleration, and make the changes necessary to speed up that code. Using a check-box menu within the GUI, you can configure processors to include features you need and remove features you don’t – options for processor interface, memories, operating system support, EDA scripts, debug and trace, and much more.
Xtensa Xplorer includes valuable tools, such as the gate count estimate, to help designers pick the best TIE instructions for their designs.
This allows Xtensa processors to be used in critical SOC functions where previously standard microprocessors or DSPs could not deliver the needed performance, throughput or low-power; and hand-coded RTL hardware blocks had to be used. And this allows Xtensa processors to be used by designers with no previous processor design experience.
Profiling Tools
Application code profiling is an extremely important tool while optimizing the performance of your application code. The Xtensa Xplorer IDE enables designers to graphically view profiling results generated by Tensilica’s pipeline-accurate ISS or by the fast functional simulator, TurboXim. Additionally, for much faster and more accurate profiling, designers can generate profiling data from hardware instantiated in an FPGA or ASIC. Designers can track performance data such instruction execution count, subroutine calls, subroutine total cycles, cache performance, branch delays, interlock cycles, and so on. Note that performance/cycle time profiling information is only available when profiling on real hardware.
While viewing functions in the profiling view, designers can also simultaneously view the assembly code in the disassembly view and the source code in the editor, both of which are annotated with the cycle count of the number of times each line of code is executed. The call graph view enables designers to view the entire application hierarchy caller and callee functions with a cycle count of the function and its callee functions.
There is also a pipeline view that displays a graphical representation of the instructions in a function as they progress through the processor pipeline. This representation is based on a dynamic trace information gathered when the application is executed on the cycle-accurate ISS. The pipeline viewer thus helps designers understand instruction stalls and latency issues