CoWare Signal Processing Designer 2009.1

Implementing Algorithms for Platform-Driven ESL Design

Highlights

• Industry's fastest, production proven signal processing simulator
• Fully supported on Windows and Linux
• 4000+ models with source code
• Unique standards reference libraries
• Fully integrated with MATLAB® and Catalytic MCS tools
• Fully integrated into CoWare platform-driven ESL design solution
• RTL cosimulation support for Cadence Incisive® and Mentor Modelsim®
• RTL code generation for Synopsys DesignCompiler® and Cadence Encounter®
• Analog-Mixed Signal (AMS) cosimulation with Cadence Incisive®
• One-click analysis
• Powerful polymodeling capability
• State-of-the-art GUI for maximum productivity
• Scalable XML database
• Automated model migration from SPW designs

Overview
CoWare® Signal Processing Designer (SPD) accelerates the design of complex, digital signal processing (DSP) systems. It is a C-based modeling and simulation environment that facilitates structured modeling and model reuse across design teams. Its efficient creation of complex DSP system models and extremely fast simulation makes Signal Processing Designer the premier choice for today's complex, multi-standard designs in the wireless and multimedia markets. It is tightly integrated with the CoWare Platform Architect and CoWare Processor Designer products.

Value
Designers of today's complex digital signal processing applications face a number of product design challenges which require unique DSP design technology. Optimization of the system cost and power consumption has the biggest impact at the highest abstraction level, where algorithms are created and optimized for the number and complexity of DSP operations needed. Differentiated algorithms determine the user experience with the final product; whether it's the impact of MIMO systems on Long-Term Evolution (LTE) wireless systems or the data rate performance for HSPA or simply the cell phone speech performance. The specific bit-accurate implementation requires not only design skills but specific DSP design tool features to achieve the best quality in the minimum amount of design time. For time to market, compliance to a particular standard is critical, since a non-compliant device is rejected by the system operator. Also, a systematic approach to verification and implementation into hardware and software is important for predicting the time to working product.

The design time and cost are also influenced greatly through a systematic approach to design reuse, which today has to start at the electronic system level (ESL) and cannot be achieved with only some coding rules for C-based modeling.

Solution
Design teams for large digital signal processing systems think in block diagrams when they specify a system. Naturally, CoWare Signal Processing Designer allows capture of the system exactly the same way--in a hierarchical block diagram editor. System designers rely on reuse of fundamental algorithms, while being adapted to specific system requirements through a set of parameters. A large library of 4000+ blocks available for CoWare Signal Processing Designer allows designers to quickly assemble the basic algorithms and set the parameters for a specific application. The way a system designer will evaluate the system performance and optimize it is typically through a large series of long simulations of the system. This requires compilation of the underlying C-models in the complex block diagram and then executing them in a specific order (also called scheduling) to produce the desired outcome. Both the optimal scheduling sequence and the optimization of individual signal processing operations, such as data-type conversions, require sophisticated techniques which are built into the CoWare Signal Processing Designer simulator. If design teams are working on a particular standard, such as HSDPA, they can rely on pre-packaged libraries provided as a reference for the standard. As opposed to individual designers exploring smaller algorithms with MATLAB®, design teams using CoWare Signal Processing Designer are working on total system design, where hundreds of complex individual algorithms have to be integrated, most likely from different designers around the world, today driven by the need for multi-standard, convergence products. Library management and control features help keep the entire design under control and tracking the design evolution as well as facilitating structured reuse of designs. Typical life cycles for important reusable models can span 5-10 years.

After initial optimization of the system using floating-point number representation, the much more involved task of specifying the system at the fixed-point level has to be performed. Customers will make use of the polymodeling feature, which allows the designer to selectively switch between floating and fixed-point representations, without changing the hierarchical block diagram. Reducing the modeling effort to a single model, which can be parameterized across the abstraction levels, is key to reducing the risk for the specification developed. The final fixed-point model is then typically run through a large number of regressions on a server farm in order to check the overall system performance under all available scenarios. Selecting the servers involved and automatically balancing the loads is enabled by configuring the interface to popular load balancing utilities.

Many sophisticated users will model as well at the C-source code level, for example to exactly mimic the production code in an embedded DSP. The interface of a C-function into the CoWare Signal Processing Designer infrastructure is very simple and makes integrating custom code, legacy models or using models as embedded C-code easy. Designers benefit from the available 4000+ models, which all come as source code and can be used as the starting point for modification.

The final verified model serves as bit-exact reference for verification of the system. Any such model can be exported as a peripheral block into a transaction-level SystemC platform into CoWare Platform Architect for usage as reference for system verification. Also, if modeled accurately, any model can be exported as a pin-level SystemC model, which either CoWare Platform Architect or leading RTL simulation products with support for SystemC IEEE 1666. If a specific part of the system is implemented as a custom processor, the processor model generated by CoWare Processor Designer can be integrated into CoWare Signal Processing Designer, thus facilitating the verification of the embedded code running on the processor against the reference model