Mentor Graphics HDL Designer Series 2009.2 combines deep analysis capabilities, advanced creation editors, and complete project and flow management, to deliver a powerful HDL design environment that increases the productivity of individual engineers and teams (local or remote) and enables a repeatable and predictable design process.
Key Benefits
Manages complex ASIC or FPGA designs in VHDL, Verilog and SystemVerilog
Accelerates RTL Reuse
Extensive design checking rules and rulesets
Interactive HDL visualization and creation tools
Automatic documentation features and reporting
Intelligent debug and analysis
Concurrent design entry and checking
Design and Reuse
Quickly assess reused code quality and increase design understanding
Efficiently create RTL designs using text, tables, and graphics
Interactively manage design flow and all project data