Software Tutorial,Education - http://www.crack-cad.com/

Sandwork设计公司以Spice波形视图工具而闻名的Sandwork设计公司，最近新推出了原理图交互探测(cross-probing)功能并发布了一款增强型可视化调试工具。 SX CDS-Link网络仿真提取(ENS)是Sandwork在现有的CDS-Link中新添的可选项，适合于Cadence设计系统公司的Virtuoso版图环境，并可以提供理想原理图和仿真波形之间的交互探测。这种相关性非常有益，因为在仿真结果中，RC网络名称是随机产生的，所以很难找到相应问题源的原始网络。 ENS选项所增加的功能正是Sandwork公司CEO Jack Yao所提到的“一对多交互探测功能”。以往，用户只能看到与每个原理图对应的一个波形，而现在，一个原理图可以与多个波形相关联。 “在复杂的设计中，当设计人员在布线后(post-layout)进行验证时，他们将面对繁杂的RC网表。”Yao指出，“设计人员很头疼如何才能把理想的原理图同大量的波形数据进行关联。利用该产品，我们能够解决这个问题。”

SX CDS-Link ENS的输入包括Cadence原理图和从任何Spice或快速Spice仿真器获得的输出。该产品与被提取出的网表相结合，目前支持Cadence的Assura和Synopsys的RCXT提取工具，还支持详细标准寄生电路格式 (DSPF)。它能对应原理图中的每一个理想网络显示多个波形。 Sandwork还对ChipView进行了增强。ChipView是一个基于布线后RC参数提取DSPF网表的可视化调试产品，它能够自动建立拓扑棍图(stick diagram)来提供一个“伪版图”视图，从“伪版图”提取出的网络可以被映射到原始网络上。 Yao介绍，一个新增加的特性就是在相同网络上，获取从任一提取节点到其它提取节点间的总阻抗的能力。另一项新的特性，是对最有可能出现问题的接地电容和耦合电容进行定位。此外，它还可以对寄生电阻进行彩色编码，以便用户找到最关键的高阻抗器件。 目前，SX CDS-Link ENS和增强型的ChipView都已经开始供货，起价分别为1,400美元和2,200美元。

::::::English Description::::::

While today’s chip designs demand increasing speed and performance, designers are also faced with the challenge of verifying their chips at both analog and logic levels expediently due to shortened product life cycle. Full-chip simulations require prudent setup and tend to create large amount of simulation data to review. Moreover, typical design process involves iterative simulations - a time consuming process.
SPICE Explorer is developed to address the newly arisen necessity for an effective transistor-level debugging environment. The tool is built upon netlist-driven debugging and visualization modules, and WaveView Analyzer with ACE scripting option completes the package. The environment provides front-to-back productivity solutions to speedup verification cycle and reduces total design cost.

Features

• Screens netlist for issues from syntax to design connectivity errors
  
• Finds error early in the verification cycle with comprehensive netlist design checker
• Examines large netlist file of millions of elements in seconds with small memory requirement
• Supports both Hspice and Spectre netlist formats
• Interactive report browser allows designers to pin point problematic devices and setup
• Netlist-driven hierarchy visualization allows intuitive hierarchy traversal
• Stimulus preview capability prior to simulation launch
• Provides interactive editing functions for PWL pattern generation
• WDF mixed-signal waveform compression technology minimizes data size and loading time
• WaveView Analyzer integrated capable of netlist cross-probing
• Analysis Command Environment (ACE) option bundled supporting Tcl/Perl

Supported Platforms

• Sun workstations – Solaris 6, 7, 8, 9, 10
• Intel x86 PC – Microsoft Windows 95/98/NT/XP
• Intel x86 PC – Linux 7.x and above
• HP-UX 11

No information