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Additional Enhancements to Quartus II Software Version 8.0

* New tasks window: Provides an interactive design flow console that guides users through the FPGA design flow.SOPC Builder: Offers support for incremental compilation and adds key intellectual property (IP) blocks to its design library, including JTAG and SPI interfaces.
* Enhanced FPGA I/O planning: Accelerates board development with added pin-swapping capabilities in the Pin Planner.
* New IP advisor: Provides design-specific guidelines and recommendations for successful use of Altera’s PCI Express and DDR3 IP.
* MegaCore® IP Library: Integrated in Quartus II software, making it easier for users to access Altera’s portfolio of IP cores. New additions with this release include PCI Express Gen2 hard IP, five new video and image processing cores and many feature enhancements.
* New megafunctions: New floating point, delay lock loop and memory initialization megafunctions in Quartus II software help speed design development.

• Altera.Quartus.II.DSP.Builder.v9.1.incl.SP2
• Altera Quartus II 9.1
• Altera Design Suite 8.0
• Altera Dsp builder 8.0
• Altera Modelsim 8.0
• Altera Megacore IP Library 7.2 SP3