Synopsys IC Compiler II (ICC2) vP-2019.03 SP1

Description

Synopsys IC Compiler II (ICC2) vP-2019.03 SP1

The Leader in Place and Route

IC Compiler™ II is the industry leading place and route solution that delivers best-in-class quality-of-results (QoR) for next generation designs across all market verticals and process technologies, while enabling unprecedented productivity. IC Compiler II includes innovative for flat and hierarchical design planning, early design exploration, congestion aware placement and optimization, clock tree synthesis, advanced node routing convergence, manufacturing compliance, and signoff closure.

Fastest Path to Design Closure

IC Compiler II is specifically architected to address aggressive performance, power, area (PPA), and time-to-market pressures of leading edge designs. Key technologies include a pervasively parallel optimization framework, multi-objective global placement, routing driven placement optimization, full flow Arc based concurrent clock and data optimization, total power optimization, multi-pattern and FinFET aware flow and machine learning (ML) driven optimization for fast and predictive design closure. Advanced Fusion technologies offer signoff IR drop driven optimization, PrimeTime® delay calculation within IC Compiler II, exhaustive path based analysis (PBA) and signoff ECO within place and route for unmatched QoR and design convergence. 

Benefits

 

Productivity

  • Highest capacity solution that supports 500M+ instances with a scalable and compact data model
  • Full suite of design planning features including transparent hierarchical optimization
  • Out of the box simple reference methodology for easy setup
  • Multi-threaded and distributed computing for all major flow steps
  • Golden signoff accuracy with direct access to PrimeTime delay calculation

PPA

  • Unified TNS driven optimization framework
  • Congestion, timing and power driven logic re-synthesis
  • IEEE 1801 UPF/multi-voltage support
  • Arc based concurrent clock and data optimization
  • Global minima driven total power optimization 

Advanced Nodes

  • Multi-pattern and FinFET aware design flow
  • Next generation advanced 2D placement and legalization
  • Routing layer driven optimization, auto NDR, and via pillar optimization
  • Machine learning driven congestion prediction and DRC closure
  • Highest level of foundry support and certification for advanced process nodes
  • IC Validator in the loop signoff driven DRC validation and fixing

Advanced Fusion Technology

  • Physically aware logic re-synthesis
  • IR drop driven optimization during all major flow steps
  • PrimeTime delay calculation based routing optimization for golden accuracy
  • Integrated PrimeTime ECO flow during routing optimization for fastest turn around time

 

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