Mentor Graphics Catapult 2011


Catapult C Synthesis Overview Reduce the Time to Verified RTL Traditional hardware design methods that require hand-written RTL development and debugging are too time-consuming and error prone for today’s complex designs. Catapult C Synthesis empowers designers to use industry standard ANSI C++ and SystemC to describe functional intent and move up to a more productive abstraction level. From these high-level descriptions, Catapult C Synthesis generates production quality RTL. Synthesizes ANSI C++ and SystemC to production quality RTL Targets algorithms, control-logic and interfaces for full-chip synthesis Dramatically shortens the path to verified RTL Making ESL Design and Verification a Reality Web Series: Join us for a for a series of complimentary web seminars that explores the many dimensions of ESL design, giving examples of how the promise of ESL is becoming a reality. Learn more High-Level Synthesis Blue Book Michael Fingeroff’s High-Level Synthesis Blue Book presents the most effective C++ synthesis coding style for achieving high quality RTL. Learn more 1 2 Catapult C Synthesis Overview Product Demo: Catapult C Synthesis Overview View Video High-Level Synthesis from ANSI C++ and SystemC Catapult offers support both for pure untimed ANSI C++ and for SystemC, the two major standard languages for high-level design and synthesis. The untimed nature of C++ makes it the best choice for architectural design and verification at the most abstract level, and SystemC is effective for the finer control desired for synthesis of complex control logic, such as bus interfaces and SoC interconnects. Control-logic, Datapath and Hierarchial Interconnects Catapult is the first solution that lets designers model, verify, and synthesize complex mixes of control and algorithmic units from a single high-level model. The tool provides dedicated support and optimizations for control-logic, datapath and interconnects, making it suitable for any type of design. With Catapult users can scale with confidence from single block designs to large-scale multi-block projects, and by doing so, tackle the design complexity of complete systems with full-chip synthesis capabilities. Front-to-Back, Fully Automated Verification Catapult integrates a robust and fully automated verification flow, helping designers confidently synthesize their designs and easily validate the correctness of the generated RTL. Starting with the input model, Catapult automatically performs linting and static code checks to catch potential errors and improve the model. Catapult also provides code coverage reports and performs runtime checks, helping designers achieve a higher degree of confidence in their C++ and SystemC code. After the RTL has been synthesized, Catapult automates a complete verification infrastructure reusing the original C++ or SystemC testbench to exercise the generated RTL. Interactive Micro-Architecture Analysis and Optimization Catapult combines automation with specific high-level constraints so designers can precisely control the hardware implementation and interactively converge on significantly better quality designs in less time. Results are displayed in a choice of X-Y plots, bar charts, tables, and schematic views. Designers quickly make informed decisions in terms of power, area, and performance to deliver the optimal balance of these features. Interface Synthesis Interfaces and their properties have a determinant impact on the performance and quality of a design. For that matter, Catapult is fully geared to help designers make the best interface decisions and build them optimally. The tool accommodates the needs of both architects seeking the best timing and bandwidth and designers needing to implement them most efficiently.


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