Intel Quartus Prime Pro Edition 18.1


Intel Quartus Prime Professional Edition 18.1


New Features and Enhancements

The Intel® Quartus® Prime Pro Edition software release version 18.1 includes the following new features and enhancements:

  • Expanded support for Intel® Stratix® 10 devices:
    • Added support for Intel® Stratix® 10 H-Tile devices.
  • Added Auto Pipelining option.
  • Added Fractal Synthesis Optimization.
  • Added new compilation strategies that you can use to help improve QoR.
  • Enhanced optimization modes.
  • Enhanced Intel® Quartus® Prime GUI:
    • Added .qdb file metadata viewer accessible from Project Navigator.
    • Added export file specification to the Design Partitions windows during flow execution.
    • Added Clock Usage Heatmap view, with the following features:
      • Shows utilization of routing and sectors.
      • Highlights the feature of a single clock.
      • Inspect a single layer with clocks distinguished by color.
    • Enhanced Chip Planner:
      • Updated element highlighting.
      • Added a "bird's eye" view.
      • Added ability to show or hide Logic Lock regions.
      • Added a new Route Reserved column.
      • Added Report Registered Connections task.
      • Added Report Clock Sector Utilization task.
      • For Intel® Stratix® 10 devices, added 50G and 100G Ethernet MAC Hard IP Block.
    • Enhanced Design Space Explorer:
      • Added graphical display of results to help you interpret results.
      • Added ability to sweep over various compilation strategies.
  • Enhanced Interface Planner:
    • Improved Intel® Quartus® Prime integration.
  • Enhanced Platform Designer:
    • Added System View tool to replace System Contents tool.
    • Reduced the time required to complete Quartus IP upgrades.
    • Added automatic system information synchronization.
    • Added limited support for ACE-Lite.
    • Enhanced support for Intel® Stratix® 10 design flows:
      • Introduced Ready Allowance for Avalon® -ST interfaces.
      • Introduced Waitrequest Allowance for Avalon® -MM interfaces.
    • Enabled the use of Verilog syntax to connect ports:
      • You can specify the port-to-port connectivity with the full breadth of Verilog operators.
      • Gives you full control over how ports are connected in the generated HDL.
      • Enables the use of arbitrary RTL and all IP in Platform Designer.
    • Added support for IP that uses System Verilog Interfaces.
  • Enhanced Advanced Link Analyzer:
    • Added Transceiver Toolkit integration.
    • Added ICN-based crosstalk simulations.
  • For Intel® Stratix® 10 devices, enhanced Rapid Recompile for the post-fit Signal Tap flow.






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