Cadence Sigrity 2015

Description

Cadence Expands Sigrity 2015 Technology Portfolio with New Products, LPDDR4 Compliance Checks, and Flexible Licensing Options The expanded Cadence® Sigrity™ technology portfolio offers: Sigrity Parallel Computing 4-pack Sigrity System Explorer, an updated power-aware system signal integrity (SI) feature Flexible purchasing options for PCB and IC package design and analysis Sigrity Parallel Computing 4-Pack Sigrity Parallel Computing 4-pack is a license that allows designers to run parallel computing tasks across four additional computers, thereby accelerating product creation time and tripling the speed of PCB extraction of signoff-accurate interconnect models. Sigrity PowerSI 3D EM Full-Wave Extraction tool Sigrity PowerSI Sigrity System Explorer Sigrity System Explorer features general-purpose topology exploration, enabling power-aware signal integrity and transient power integrity (PI) analysis across multiple fabrics. It can be used for what-if analysis of signals, power, or both signals and power together. The software enables signal and power integrity analysis using interconnect models that are pre-route (what-if), captured from measurement, or extracted using electromagnetic field (EM) tools such as Cadence Sigrity PowerSI® or Sigrity PowerSI 3D EM Full-Wave Extraction tools. Sigrity System Explorer Power-Aware System Signal Integrity Support for LPDDR4 The power-aware system signal integrity (SI) feature now supports LPDDR4 analysis with full JEDEC compliance checking, including bit-error rate analysis with high capacity channel simulation for memory interface. LPDDR4 support Sigrity System SI technology Product Bundle Options Cadence product bundles provide flexible licensing options for small analysis teams with big analysis requirements. These bundles include: Combined license for Allegro® Sigrity SI and Allegro Sigrity PI base products, when a single user is responsible for both SI and PI tasks. Combined System SI license for both Serial Link and Parallel Bus analysis, when a single user is responsible for both memory interfaces and SerDes interfaces.

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