Cadence Innovus v15.10.000


Cadence Innovus v15.10.000 Meet PPA and TAT Requirements at Advanced Nodes How are you managing conflicts between power, performance, and area (PPA) goals and turnaround time (TAT) demands? Ready for a better way? Turn to the Cadence® Innovus™ Implementation System, a physical implementation tool that delivers typically 10-20% production-proven power, performance, and area (PPA) advantages along with up to 10X TAT gain at advanced 16/14/10nm FinFET designs as well as at established processes. The Innovus Implementation System is optimized for industry-leading embedded processors, as well as for 16nm, 14nm, and 10nm processes, helping you get an earlier design start with a faster ramp-up. With unique new capabilities in placement, optimization, routing, and clocking, the Innovus Implementation System features an architecture that accounts for upstream and downstream steps and effects in the design flow. This architecture minimizes design iterations and provides the runtime boost you’ll need to get to market faster. Using the Innovus Implementation System, you’ll be equipped to build integrated, differentiated systems with less risk. The new GigaPlace solver-based placement technology provides optimal pipeline placement, wire length, utilization, and PPA. This technology is slack-driven and topology-, pin access- and color-aware. GigaPlace in Action: Learn how solver-based placement technology works Watch video » The GigaPlace engine employs a global optimization strategy and a numerical solver to avoid the trap of local minima. This approach results in globally optimal PPA by reducing design iterations between different steps in the flow.


  • Previous:Cadence Allegro and OrCAD 17.00.001 Hotfix
  • Next:Cadence Allegro and OrCAD 17.00.003 Hotfix
  • Letters A B C D E F G H I J K L M N O P Q R S T U V W X Y Z TOP