Cadence INCISIVE 15.20.001 Linux


Cadence INCISIVE Cadence Design Systems, Inc., a leader in global electronic design innovation, introduced its leading functional verification platform and methodologies, INCISIVE 15.20. As electronic products across all market segments become more sophisticated, developing their underlying hardware and software, and integrating the two sides, continues to grow more complex. Early software development, hardware verification, hardware/software integration, and integrated system validation have become primary challenges, increasing development costs, project schedules, and risks. Using the Cadence Verification Suite, you can reduce system integration time by up to 50%, accelerating intellectual property (IP) development, system-on-chip (SoC) integration, and concurrent hardware/software development. This verification suite is comprised of core engines, verification fabric technologies, and solutions spanning these technologies, as shown in Figure 1. Core engines include JasperGold formal verification, RocketSim and Incisive simulation, Palladium® emulation, and Protium FPGA prototyping. We developed each engine to provide best-in-class technology. Verification fabric technologies include Verification IP, Incisive vManager planning and metrics, Indago debug solutions, and Perspec software-driven testing. We developed these technologies to provide a flow-driven multi-engine verification environment. Solutions in the suite include total throughput for the shortest project schedule, metric-driven signoff for quality, and an application-centric focus to meet the needs of products for mobile, networking and servers, automotive, consumer and the Internet of Things (IoT), aerospace and defense, and other vertical segments. Our Verification Suite technologies, flows, and solutions support a broad range of industry standards, are open for third-party integration, and are further augmented by our ecosystem partners, including ARM and many others.


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