Cadence ASI v16.60.004 Win32&Win64


In this course, you use the Allegro® Sigrity™ SI software to develop design rules for high-speed designs. You add the resulting physical and electrical constraints to the design through topology templates. These constraints drive the routing of nets on the printed circuit board. You run preroute and postroute signal simulations to analyze the PCB for reflection, crosstalk, and other high-speed design factors Learning Objectives After completing this course, you will be able to: o Create, extract, and explore topologies o Run solution space analysis o Create an electrical constraint set o Apply constraints to drive placement and routing o Run postroute DRC check o Use template revision to update the ECSet applied to the nets o Analyze nets on the routed board design for signal integrity o Create a DesignLink between boards and use it to run multiboard simulation Software Used in This Course o Allegro Sigrity SI Base Software Release(s) o ASI 16.6, SPB 16.6 Modules in this Online Course o Introduction to Allegro Sigrity SI o Simulation Model Assignment o Topology Extraction o SigXplorer Basics o Sweep Simulations and Constraint Setting with SigXplorer o Constraint Floorplanning o DesignLink Creation o Postroute Analysis o Impedance and Coupling Checking o Differential Pairs o The EMS2D Field Solver Audience o Electrical Engineers o PCB Designers


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